Typical prior art techniques, wherein data is transferred directly between one or more functional devices such as terminals and a main memory of the system, include cycle steal and direct memory access (DMA). In the cycle steal technique, I/O data is transferred by stealing a memory cycle of a processor. An address counter and a data transfer bus are shared by the processor and the devices. Therefore, in the cycle steal technique, little hardware has to be added, but a problem of conflict in the use of the bus remains.
On the other hand, in the DMA technique, the I/O data is transferred through an additional data bus separate from a Processor Input/Output (PIO) bus which is used for transferring device addresses, I/O commands, I/O interrupt requests, etc. Also, an additional address counter is usually employed instead of the processor address counter. The DMA control circuit including such an address counter has been conventionally located in a functional device, but as the number of connected functional devices is increased, it is desirable that all the functional devices are controlled by a shared memory access control circuit as disclosed, for example, in Japanese Published Unexamined Patent Application No. 52-117536.
Further, Japanese Published Unexamined Patent Applications No. 52-20729, 52-79629 and 54-5637, disclose memory addressing wherein a pointer table capable of retaining a plurality of memory addresses is provided and a memory is addressed by accessing a certain entry of the pointer table using an assigned entry identifier, and loading its content or memory address into an address counter.
However, in any of these prior art techniques, the processor executes every data transfer from a functional device to the memory or from the memory to the functional device. Therefore, when successive transfer operations are required in which a certain functional device writes its data into the memory and then a different functional device reads the same data out of the memory, the processor has to issue a command for both transfers. Systems, in which such successive transfer operations are repeatedly required, include facsimile systems, for example. When the facsimile system transmits image data, the image data is first written into a buffer memory and then read out to a compressor, where the data is compressed according to a given algorithm. The compressed data is then written into the buffer memory. Finally, the compressed data in the buffer memory is read out to a communication device from which the data is transmitted to a remote facsimile system or a store-and-forward apparatus. In a receive operation, the data is transferred sequentially from the communication device to the buffer memory, then from the buffer memory to a decompressor, then from the decompressor to the buffer memory, and finally from the buffer memory to a printer.
In a program controlled facsimile system, if the data transfer starting from the scanner and ending at the communication device and the data transfer starting from the communication device and ending at the printer can be performed without the intervention of the processor, it is apparent that total transfer time would be shortened and the load on the processor would be reduced. This is also true for other data processing systems where data transfers between I/O adapters or terminal units are required.